ALUs are widely used in central processing units of data processing systems including but not limited to microprocessors. As is well known to those having skill in the art, an ALU is the unit that performs arithmetic commands, such as adding, subtracting, multiplying and dividing, and logical commands such as OR, AND and NOT. As the speed of data processing systems continues to increase, and the integration density of integrated circuits continues to grow, it is generally desirable to provide high speed ALUs that can consume reduced area in an integrated circuit.
As is well known to those having skill in the art, an ALU generally includes a plurality of input multiplexers that are responsive to a function selection signal. The function selection signal indicates which one of a predetermined number of logical functions is to be performed. Each input multiplexer is coupled to at least two data input signals, so that the function selection signal causes the input multiplexer to produce a selected logical function of the data input signals. A plurality of adders are responsive to the plurality of input multiplexers, to perform addition on the selected logical function of the data input signals.
More specifically, ALUs may be designed in a bit-slice implementation wherein an input multiplexer and an adder are responsive to a predetermined bit of first and second data input signals. Each of the input multiplexers is responsive to the function selection signal, to produce the selected logical function of the associated bit. Each adder is coupled to a corresponding multiplexer, and the carry output of a preceding adder is coupled to the carry input of a succeeding adder. Accordingly, an input multiplexer and an adder may be provided for each bit of data input signal, from a least significant bit (LSB) to a most significant bit (MSB). The adders are interconnected so that the carry input of a given bit is connected to the carry output of a preceding bit.
It will be understood that in order to perform the entire set of sixteen arithmetic and logical functions of two bits, each input multiplexer may comprise a plurality of input multiplexers, and the function selection signal may be a four-bit function selection signal that is coupled to the multiplexers. The design of an ALU as described above is well known to those having skill in the art. See for example, the textbook entitled "Digital Engineering Design, a Modern Approach" by Richard F. Tinder, Prentice-Hall, 1991, pp. 275-277, the disclosure of which is hereby incorporated herein by reference.
Notwithstanding the above-described ALU design, it is generally desirable to allow further increases in ALU speed and integration density.